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over current event is typically 120ns and the switch
will latch off until reset by bringing this input high or
recycling of the input power.
Figure 4: Over current trip vs. sense resistor over
temperature.
VC Voltage Regulator and MOSFET Drive:
The biasing scheme in the PI2161 uniquely enables
the gate control relative to the PG pin via the resistor
R PG shown in Figure 1. The VC input provides power
to the control circuitry, the charge pump and the gate
driver. An internal regulator clamps the VC voltage to
11.7V with respect to PG.
of the MOSFET. The VC pin will be biased through
the load potential once the MOSFET is enabled.
In a high voltage application as shown in Figure 1 the
lower bias resistor R PG placed between the PG pin
and system ground is required. R PG creates an offset
voltage at the PG pin to regulate VC with respect to
PG when the MOSFET is enabled and the load
voltage reaches the input voltage.
The PI2161 has an integrated charge pump that
approximately doubles the regulated VC with respect
to PG enhancing the N-Channel MOSFET gate to
source voltage.
The internal gate driver controls the N-channel
MOSFET such that in the on state, the gate driver
applies current to the MOSFET gate driving it to bring
the load up to the input voltage and into the R DS(on)
condition.
When an over current condition is sensed the gate
driver pulls the gate low to PG and discharges the
MOSFET gate with 4A peak capability.
Load Status: (VO)
When the Gate is enabled, a 150k ? resistor is
connected to the MOSFET source and VO. An
external resistor between VO and ground creates a
voltage divider that scales the load voltage down to
the desired level to interface with the diagnostic circuit
to represent a logic state or analog voltage level. The
external resistor R VO can be calculated using the
following equation:
The internal regulator circuit has a comparator to
monitor VC voltage and pulls the gate low when VC to
PG is lower than the VC Under-Voltage Threshold.
R VO ? 150 K ? ?
VO
V SH ? VO
During start up or in a fault condition when the output
(Load) is shorted, the VC pin is biased through a
10KΩ (R D-VC ) internal resistor connected to the drain
Picor Corporation ? pi corpower.com
Where:
VO :
V SH :
PI2161
Desired voltage level at VO pin
Enabled load or SH voltage
Rev 1.1 , Page 6 of 18
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